Patent Number: 6,967,130

Title: Method of forming dual gate insulator layers for CMOS applications

Abstract: A method of forming dual gate insulator layers, each with a specific insulator thickness, featuring a HF type pre-clean procedure performed prior to formation of each of the gate insulator layers, has been developed. After a first HF type pre-clean procedure a silicon nitride layer is deposited on the native oxide free, semiconductor substrate followed by selective removal of silicon nitride layer from a second portion of the semiconductor substrate. After a second HF type pre-clean procedure a silicon dioxide gate insulator layer is formed on the second portion of the native oxide free, semiconductor substrate, with the silicon dioxide gate insulator layer comprised with a different thickness than the silicon nitride gate insulator layer, located on a first portion of the semiconductor substrate. The procedure used to form the silicon dioxide gate insulator layer also removes bulk traps in the silicon nitride gate insulator layer.

Inventors: Chen; Chi-Chun (Kaohsiung, TW), Lee; Tzu-Liang (Hsinchu, TW), Chen; Shih-Chang (Hsin-Chu, TW)

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.

International Classification: H01L 21/70 (20060101); H01L 21/8238 (20060101); H01L 021/8238 (); H01L 021/31 (); H01L 021/302 ()

Expiration Date: 1/22/02018