Patent Number: 6,967,133

Title: Method for fabricating a semiconductor structure

Abstract: The present invention provides a method for fabricating a semiconductor structure having a plurality of gate stacks (GS1, GS2, GS3, GS4) on a semiconductor substrate (10), having the following steps: application of the gate stacks (GS1, GS2, GS3, GS4) to a gate dielectric (11) above the semiconductor substrate (10); formation of a sidewall oxide (17) on sidewalls of the gate stacks (GS1, GS2, GS3, GS4); application and patterning of a mask (12) on the semiconductor structure; and implantation of a contact doping (13) in a self-aligned manner with respect to the sidewall oxide (17) of the gate stacks (GS1, GS2) in regions not covered by the mask (12).

Inventors: Amon; Jurgen (Dresden, DE), Faul; Jurgen (Radebeul, DE), Gruening; Ulrike (Munchen, DE), Jakubowski; Frank (Dresden, DE), Schuster; Thomas (Dresden, DE), Strasser; Rudolf (Hsin Chu, TW)

Assignee: Infineon Technologies AG

International Classification: H01L 21/70 (20060101); H01L 21/8242 (20060101); H01L 21/8238 (20060101); H01L 021/8238 ()

Expiration Date: 1/22/02018