Patent Number: 6,967,143

Title: Semiconductor fabrication process with asymmetrical conductive spacers

Abstract: A semiconductor process and resulting transistor includes forming conductive extension spacers (146, 150) on either side of a gate electrode (116). Conductive extensions (146, 150) and gate electrode 116 are independently doped such that each of the structures may be n-type or p-type. Source/drain regions (156) are implanted laterally disposed on either side of the spacers (146, 150). Spacers (146, 150) may be independently doped by using a first angled implant (132) to dope first extension spacer (146) and a second angled implant (140) to dope second spacer (150). In one embodiment, the use of differently doped extension spacers (146, 150) eliminates the need for threshold adjustment channel implants.

Inventors: Mathew; Leo (Austin, TX), Muralidhar; Ramachandran (Austin, TX)

Assignee: Freescale Semiconductor, Inc.

International Classification: H01L 21/265 (20060101); H01L 21/336 (20060101); H01L 29/66 (20060101); H01L 29/78 (20060101); H01L 21/02 (20060101); H01L 021/336 ()

Expiration Date: 1/22/02018