Patent Number: 7,029,591

Title: Planarization with reduced dishing

Abstract: A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.

Inventors: Catabay; Wilbur G. (Saratoga, CA), Hsia; Wei-Jen (Saratoga, CA), Cui; Hao (Gresham, OR)

Assignee: LSI Logic Corporation

International Classification: B44C 1/22 (20060101)

Expiration Date: 4/18/02018