Patent Number: 7,042,027

Title: Gated lateral thyristor-based random access memory cell (GLTRAM)

Abstract: One aspect of the present subject matter relates to a memory cell, or more specifically, to a scalable GLTRAM cell that provides DRAM-like density and SRAM-like performance. According to various embodiments, the memory cell includes an access transistor and a gated, lateral thyristor integrally formed above the access transistor. The access transistor has a drain region, a raised source region, and a gate. The thyristor has a first end that is formed with the raised source region of the access transistor. In various embodiments, the lateral thyristor is fabricated using a metal-induced lateral crystallization technique (MILC) adopted for thin-film-transistor (TFT) technology. In various embodiments, the stacked lateral thyristor is integrated by raising the source region of the access transistor using a selective epitaxy process for raised source-drain technology. Other aspects are provided herein.

Inventors: Bhattacharyya; Arup (Essex Junction, VT)

Assignee: Micron Technology, Inc.

International Classification: H01L 29/45 (20060101); H01L 29/32 (20060101); H01L 29/43 (20060101); H01L 29/51 (20060101)

Expiration Date: 5/09/02018