Patent Number: 7,042,052

Title: Transistor constructions and electronic devices

Abstract: The invention includes a non-volatile memory cell comprising a field effect transistor construction having a body region within a crystalline material. The body region includes a charge trapping region. The memory cell can be TFT-SOI based, and can be supported by a substrate selected from a diverse assortment of materials. The top portion of the substrate can be a conductive layer separated from the memory device by the SOI-oxide insulator film. The charge trapping region can be, for example, silicon enriched silicon nitride or silicon enriched silicon oxide. The crystalline material can include silicon and germanium. The transistor comprises first and second diffusion regions within the body region, and also comprises a channel region between the first and second diffusion regions. The entirety of the body region within the crystalline material can be within a single crystal of the material.

Inventors: Bhattacharyya; Arup (Essex Junction, VT)

Assignee: Micron Technology, Inc.

International Classification: H01L 27/01 (20060101)

Expiration Date: 5/09/02018