Patent Number: 7,042,069

Title: Semiconductor device and method of manufacturing same, wiring board, electronic module, and electronic instrument

Abstract: A plurality of leads includes a plurality of lead groups, each of which are formed of at least two first leads, and a plurality of second leads. Each of the second leads is positioned between an adjacent pair of the lead groups. Each of an outermost pair of the first leads of each of the lead groups includes a first portion and a second portion, the first portion of each of the outermost pair of the first leads being positioned at a first spacing apart and the second portion of each of the outermost pair of the first leads being positioned at a second spacing apart which is smaller than the first spacing. Each of the second leads is disposed in a manner to avoid a region that is sandwiched between the first portion of each of the adjacent pair of the lead groups and has a portion that is disposed in a region that is sandwiched between the second portion of each of the adjacent pair of the lead groups.

Inventors: Urushido; Tatsuhiro (Sakata, JP)

Assignee: Seiko Epson Corporation

International Classification: H01L 23/495 (20060101)

Expiration Date: 5/09/02018