Patent Number: 7,042,085

Title: Method for packaging electronic modules and multiple chip packaging

Abstract: A method for packaging electronic assemblies and a multiple chip package, at least one power semiconductor chip being applied to a base plate using a first solder, at least one logic chip being applied to the base plate, the logic chip and the base plate being positioned electrically insulated from one another, at least one logic chip being connected to the at least one power semiconductor chip using signal transmission lines, and the electronic assembly including the at least one power semiconductor chip and the at least one logic chip being packaged using a molding compound in order to provide a multiple chip package.

Inventors: Wolf; Kuno (Jungingen, DE), Ernst; Stephan (Odfildern, DE), Plikat; Robert (Ummern, DE), Feiler; Wolfgang (Reutlingen, DE)

Assignee: Robert Bosch GmbH

International Classification: H01L 23/34 (20060101)

Expiration Date: 5/09/02018