Patent Number: 7,042,094

Title: Via structure for semiconductor chip

Abstract: A multi-level via structure for a semiconductor chip in which the collective area of a vias structure is not entirely oriented directly in-line with the collective area of an adjacent vias structure. In one embodiment, adjacent via structure areas appear to be crisscrossed in relation to one another and in another embodiment adjacent via structure areas do not coincide at all from a perpendicular perspective.

Inventors: Kothandaraman; Chandrasekharan (Wappingers Falls, NY)

Assignee: Infineon Technologies AG

International Classification: H01L 23/48 (20060101); H01L 23/52 (20060101); H01L 29/40 (20060101)

Expiration Date: 5/09/02018