Patent Number: 7,042,097

Title: Structure for reducing stress-induced voiding in an interconnect of integrated circuits

Abstract: A structure for reducing stress-induced voiding in an interconnect of an integrated circuit, the interconnect having a first portion and at least a second portion narrower than the first portion. The structure comprises at least one interior slot disposed in the first portion in proximity to the intersection of the first portion and the second portion. The present invention also includes methods of making the interconnect and the structure. A conductive interconnect structure comprises a first portion and at least a second portion narrower than the first portion; and a stress reducing structure comprising a transition portion formed at an intersection of the first portion and the second portion.

Inventors: Yao; Chih-Hsiang (Taipei, TW), Hsia; Chin-Chiu (Taipei, TW), Wan; Wen-Kai (Hsinchu, TW)

Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.

International Classification: H01L 23/48 (20060101); H01L 23/52 (20060101); H01L 29/40 (20060101)

Expiration Date: 5/09/02018