Patent Number: 7,042,098

Title: Bonding pad for a packaged integrated circuit

Abstract: An integrated circuit is packaged using a package substrate that has a bottom side with a regular array of connection points and a top side with the integrated circuit on it. Vias in the package substrate provide electrical connection between the top and bottom sides. The vias have a via capture pad to which a wire may be wire bonded so that the wires from the IC to the substrate top side directly contact the vias at their capture pads without the need for traces from a top side bond pad to a via. The via capture pad is shaped to include at least one sharp edge to improve the ability of a wirebonder with pattern recognition software to locate the capture pad and place the wire.

Inventors: Harun; Fuaida (Selangor, MY), Koh; Liang Jen (Selangor, MY), Tan; Lan Chu (Selangor, MY)

Assignee: Freescale Semiconductor,INC

International Classification: H01L 23/02 (20060101); H01L 23/48 (20060101); H01L 23/52 (20060101)

Expiration Date: 5/09/02018