Patent Number: 7,042,103

Title: Low stress semiconductor die attach

Abstract: A semiconductor device (121) is provided which comprises a substrate and a die (123) having a first surface which is attached to the substrate by way of a die attach material. At least a portion (127) of the perimeter of the die is resistant to wetting by the die attach material, either through treatment with a dewetting agent or by selective removal of the backside metallization. It is found that this construction allows the surface area of the die to be increased without increasing the incidence of cracking and chipping along the sawn edges of the die.

Inventors: Condie; Brian W. (Mesa, AZ), Dougherty; David J. (Tempe, AZ)

Assignee: Motorola, Inc.

International Classification: H01L 23/52 (20060101)

Expiration Date: 5/09/02018