Patent Number: 7,042,260

Title: Low power and low timing jitter phase-lock loop and method

Abstract: A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output clock signal is generated by a voltage controlled oscillator having a control input coupled to receive an output from the phase detector, and a frequency multiplier coupled to the output of the voltage controlled oscillator. As a result, the CLK.sub.OUT signal generated by the frequency multiplier has a relatively high frequency while the voltage controlled oscillator, by operating at a relatively low frequency, uses relatively little power.

Inventors: Choi; Dong Myung (Boise, ID)

Assignee: Micron Technology, Inc.

International Classification: H03L 7/06 (20060101)

Expiration Date: 5/09/02018