Patent Number: 7,042,265

Title: Interlaced delay-locked loops for controlling memory-circuit timing

Abstract: For control, some memory circuits use a delay-locked loop to generate a set of signals, each delayed a different amount relative a reference signal. However, as circuits get faster and faster, conventional delay-locked loops require use of extra interpolation circuitry to generate smaller delays, and thus consume considerable power and circuit space. Accordingly, the inventor devised a circuit which interlaces and synchronizes two delay-locked loops, each including a number of controllable delay elements linked in a chain. In one embodiment, the first loop produces a sequence of clock signals delayed an even number of delay periods relative a reference clock signal, and the second loop produces a sequence of clock signals delayed an odd number of delay periods relative the reference clock signal. In addition, the first and second loops are synchronized.

Inventors: Harrison; Ronnie M. (Boise, ID)

Assignee: Micron Technology, Inc.

International Classification: H03H 11/26 (20060101)

Expiration Date: 5/09/02018