Patent Number: 7,042,269

Title: Method for dynamic balancing of a clock tree

Abstract: The present invention provides a method to balance a clock tree dynamically. A controllable buffer is inserted in a specific level of a clock tree, and a controller is provided for adjusting two clocks with different skew by controlling the PMOS/NMOS arrangements in the controllable buffer so as to generate more current for compensating the time delay of slow clock to a sink. This method effectively suppressed the clock skew generated by the voltage drop or the temperature variations in the synchronous logic circuit design.

Inventors: Kao; De Yu (Taipei, TW)

Assignee: Princeton Technology Corporation

International Classification: G06F 1/04 (20060101)

Expiration Date: 5/09/02018