Patent Number: 7,042,277

Title: Circuit and method for reducing jitter in a PLL of high speed serial links

Abstract: Aspects for reducing jitter in a PLL of a high speed serial link include examining at least one parameter related to performance of a voltage controlled oscillator (VCO) in the PLL, and controlling adjustment of a supply voltage to the VCO based on the examining. A regulator control circuit performs the examining and controlling.

Inventors: Cranford, Jr.; Hayden C. (Cary, NC), Garvin; Stacy J. (Durham, NC), Norman; Vernon R. (Cary, NC), Rasmus; Todd M. (Cary, NC)

Assignee: International Business Machines Corporation

International Classification: G01F 1/10 (20060101)

Expiration Date: 5/09/02018