Patent Number: 7,042,381

Title: Delay equalized Z/2Z ladder for digital to analog conversion

Abstract: A Z/2Z ladder network includes an R/2R ladder network having capacitors coupled across series resistors within the R/2R ladder network, wherein the capacitors are sized to substantially match delays from nodes within the ladder network to an output node. The Z/2Z ladder network can be implemented within a digital to analog controller ("DAC"), including higher resolution DACs, and high data rate DACs. In higher resolution DACs, and high data rate DACs, the Z/2Z ladder network is coupled through switches to corresponding current sources. The Z/2Z ladder is optionally implemented differentially.

Inventors: Pan; Hui (Irvine, CA)

Assignee: Broadcom Corporation

International Classification: H03M 1/78 (20060101)

Expiration Date: 5/09/02018