Patent Number: 7,042,747

Title: Ternary CAM bitcells

Abstract: Two new ternary CAM bitcell design options are presented that provide compact layout solutions while maximizing matchline channels routing through the cells. In both layouts, the first inventive layout, an asymmetric layout of the 6T-SRAM bitcell is used to improve ease of layout, density, and performance of ternary CAM cells. In the second inventive layout, n-type diffusions for the SRAM bitcell and the comparison circuit are separated, creating a bitcell having a more even cell aspect ratio.

Inventors: Castagnetti; Ruggero (Menlo Park, CA), Venkatraman; Ramnath (San Jose, CA), Glenn; Joseph E. (Eden Prairie, MN)

Assignee: LSI Logic Corporation

International Classification: G11C 15/00 (20060101)

Expiration Date: 5/09/02018