Patent Number: 7,042,964

Title: Viterbi decoder, method and unit therefor

Abstract: A Viterbi decoder includes a number of classical Add-Compare-Select units and a number of further Add-Compare-Select unit having a lower complexity butterfly unit (300) having only two adder means, such that the further Add-Compare-Select unit has a butterfly unit (300) comprising: first adder means (310) for receiving a first path metric and a branch metric and for producing at its output the addition thereof; and second adder means (320) for receiving a second path metric and said branch metric and for producing at its output the addition thereof. First comparator means (330) are coupled to receive the output of the second adder means and coupled to receive the first path metric for comparing therebetween. Second comparator means (340) are coupled to receive the output of the first adder means and coupled to receive the second path metric for comparing therebetween. First selection means (350) for selecting between the second adder means output and the first path metric produce a first survivor path metric in dependence on the first comparator means comparison. Second selection means (360) for selecting between the first adder means output and the second path metric signal produce a second survivor path metric in dependence on the second comparator means comparison. Only two adder means are used for processing metric transitions as a second branch metric is identified as having a value of zero.

Inventors: Muck; Markus (Paris, FR), Hekmann; Ralf (Ferney-Voltaire, FR)

Assignee: Freescale Semiconductor, Inc.

International Classification: H03D 1/00 (20060101); H04L 27/06 (20060101)

Expiration Date: 5/09/02018