Patent Number: 7,043,595

Title: Data transfer control device

Abstract: Even when an S-PCI bus 1b requests transfer while a P-PCI bus 1a is executing burst transfer, assert of a TRDY# signal for data transfer of the P-PCI side is delayed so that next data transfer of the P-PCI side is completed within 8 clock cycles since the TRDY# signal for data transfer of the P-PCI side is asserted.

Inventors: Kawai; Hideki (Takatsuki, JP)

Assignee: Matsushita Electric Industrial Co., Ltd.

International Classification: G06F 13/36 (20060101)

Expiration Date: 5/09/02018