Patent Number: 7,043,673

Title: Content addressable memory with priority-biased error detection sequencing

Abstract: A content addressable memory (CAM) device having circuitry to generate a biased sequence of addresses. A first counter circuit increments an address value in response to a clock signal and resets the address value to a start address in response to a control signal. A second counter increments a limit value in response to a control signal. A compare circuit compares the address value and the limit value and, if the address value and the limit value have a predetermined relationship, asserts the control signal.

Inventors: Ichiriu; Michael E. (Cupertino, CA), Srinivasan; Varadarajan (Los Altos Hills, CA)

Assignee: NetLogic Microsystems, Inc.

International Classification: G11C 29/00 (20060101)

Expiration Date: 5/09/02018