Patent Number: 7,043,707

Title: Simulation result verification method and simulation result verification device

Abstract: A simulation result verification method of the present invention compares a simulation result representing the relationship between the time and the output state at a given node, with condition information specifying the conditions for the output state of the given node over time, and evaluates the same. Accordingly, it is possible to determine whether the simulation result and the condition information agree with each other and it is not necessary to visually verify the relationship between the simulation result and the threshold value, thereby shortening the verification time and reducing possible errors in visual verification to a low level.

Inventors: Takatsuki; Naohisa (Osaka, JP)

Assignee: Matsushita Electric Industrial Co., Ltd.

International Classification: G06F 17/50 (20060101); G06F 9/45 (20060101)

Expiration Date: 5/09/02018