Patent Number: 7,045,834

Title: Memory cell arrays

Abstract: A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted portions that intersect a corresponding portion of an active area line at an angle. Contacts electrically coupling the bit line to portions of the active area line are formed in a region generally defined by the angled intersection of the bit line to the active area line. The memory cells can have an area of about 6F.sup.2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line includes a first level portion and a second level portion.

Inventors: Tran; Luan (Meridian, ID), Duncan; D. Mark (Boise, ID), Lowrey; Tyler A. (Boise, ID), Kerr; Rob B. (Boise, ID), Brown; Kris K. (Garden City, ID)

Assignee: Micron Technology, Inc.

International Classification: H01L 27/10 (20060101); H01L 29/76 (20060101); H01L 29/94 (20060101); H01L 31/062 (20060101); H01L 31/113 (20060101)

Expiration Date: 5/16/02018