Patent Number: 7,047,174

Title: Method for producing test patterns for testing an integrated circuit

Abstract: A test pattern generation flow has a stimulus and a device under test (DUT) that operate together through a test bench. The test bench monitors and collects all the data necessary to generate a test program. This information is presented as a captured simulation that allows for ease of generating test software, as well as other simulations such as fault simulation and virtual test simulation. The complete and convenient information can be utilized to automate the development and/or easily manually develop and debug the test software.

Inventors: Koh; Alex S. Y. (Austin, TX), Carlin; Alan Joseph (Austin, TX), Tumin; Kenneth Paul (Austin, TX), Carson, Jr.; Hubert Glenn (Austin, TX)

Assignee: Freescale Semiconductor, Inc.

International Classification: G06F 9/455 (20060101)

Expiration Date: 5/16/02018