Patent Number: 7,084,962

Title: Method for detecting positioning errors of circuit patterns during the transfer by means of a mask into layers of a substrate of a semiconductor wafer

Abstract: A method, suitable to photolithographie projection, for detecting the positioning errors of circuit patterns during the transfer by a mask into layers of a substrate of a semiconductor wafer. After the transfer of at least one multiple arrangement of a first test structure into at least one resist layer above the substrate, wherein the first test structure includes a first circuit pattern, at least one first overlay mark and at least one first micropatterned alignment mark, the values of a first positioning error of the first circuit patterns relative to the first overlay marks and the first micropatterned alignment marks are determined for each element of the at least one multiple arrangement.

Inventors: Bauch; Lothar (Dresden, DE), Gruss; Stefan (Dresden, DE), Teipel; Ansgar (Dresden, DE), Froehlich; Hans-Georg (Dresden, DE)

Assignee: Infineon Technologies AG

International Classification: G03B 27/32 (20060101); G03B 27/52 (20060101); G03F 7/20 (20060101); G03F 9/00 (20060101)

Expiration Date: 8/01/02018