Patent Number: 7,085,152

Title: Memory system segmented power supply and control

Abstract: A memory device having memory cells supplied with a separate higher voltage power than the separate power supplied to memory logic, and a lower power state that entails removing power from at least some of the logic such that refresh operations to preserve the contents of the memory cells continue to take place, but at least some of the interface to the memory device is powered down to reduce power consumption.

Inventors: Ellis; Robert M. (Hillsboro, OR), Mooney; Stephen R. (Beaverton, OR), Kennedy; Joseph T. (Beaverton, OR)

Assignee: Intel Corporation

International Classification: G11C 11/24 (20060101)

Expiration Date: 8/01/02018