Patent Number: 7,085,164

Title: Programming methods for multi-level flash EEPROMs

Abstract: A method is provided for programming a memory cell of an electrically erasable programmable read only memory. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a selected constant drain-to-source bias voltage and a selected gate voltage.

Inventors: Chen; Chun (Boise, ID), Prall; Kirk D. (Boise, ID)

Assignee: Micron Technology, Inc.

International Classification: G11C 11/34 (20060101); G11C 16/04 (20060101)

Expiration Date: 8/01/02018