Patent Number: 7,085,166

Title: Semiconductor memory device and programming method thereof

Abstract: A semiconductor memory device includes: a plurality of nonvolatile memory cells; a first load cell for generating a read voltage relative to a read current during reading from a selected nonvolatile memory cell; a reference cell for storing a reference state corresponding to a reference current of the selected nonvolatile memory cell; a second load cell for generating a voltage based on the reference current through the reference cell; and a programming circuit for generating a reference voltage equal to a voltage obtained from a specific current-voltage characteristic of the first load cell with respect to the reference current and programming the reference cell so as to equalize the voltage of the second load cell with the reference voltage, thereby to compensate for variations in the first load cell. And each of the nonvolatile memory cell includes a gate electrode formed on a semiconductor layer via a gate insulating film, a channel region disposed under the gate electrode, diffusion regions disposed on both sides of the channel region and having a conductive type opposite to that of the channel region, and memory functional units formed on both sides of the gate electrode and having a function of retaining charges.

Inventors: Iwase; Yasuaki (Tenri, JP), Yaoi; Yoshifumi (Yamatokoriyama, JP), Iwata; Hiroshi (Nara, JP), Shibata; Akihide (Nara, JP), Morikawa; Yoshinao (Ikoma, JP), Nawaki; Masaru (Nara, JP)

Assignee: Sharp Kabushiki Kaisha

International Classification: G11C 16/06 (20060101)

Expiration Date: 8/01/02018