Patent Number: 7,085,187

Title: Semiconductor storage device

Abstract: A semiconductor storage device in which the chip area is prevented from increasing to reduce the leakage current during low power (power down) time caused by shorting across bit and word lines due to crossing failure. There are provided precharge equalizing NMOS transistors the gates of which are supplied with a control signal (BLEQT). These precharge equalizing NMOS transistors are connected across a power supply line (VNLR), supplying a precharge potential to the bit line, and the bit line. At the time of low power operation, a potential (0.7 to 1.4V) lower than the potential VPP (e.g. 3.2V) applied during the precharge operation of the normal operation is supplied to the gate terminals of the transistors to reduce the leakage current caused by shorting across the bit and word lines caused in turn by crossing failure.

Inventors: Koshikawa; Yasuji (Tokyo, JP), Dono; Chiaki (Tokyo, JP)

Assignee: Elpida Memory, Inc.

International Classification: G11C 5/14 (20060101)

Expiration Date: 8/01/02018