Patent Number: 7,085,794

Title: Low power vector summation method and apparatus

Abstract: An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.

Inventors: Azadet; Kameran (Morganville, NJ), Yu; Meng-Lin (Morganville, NJ), Yu; Zhan (Sunnyvale, CA)

Assignee: Agere Systems Inc.

International Classification: G06F 7/38 (20060101); G06F 17/10 (20060101)

Expiration Date: 8/01/02018