Patent Number: 7,085,941

Title: Clock control apparatus and method, for a memory controller, that processes a block access into single continuous macro access while minimizing power consumption

Abstract: A clock control apparatus for a memory controller comprises an interface unit which processes a block access to a plurality of banks of an SDRAM as a single continuous macro access in order to perform arbitration of the macro access, the block access externally supplied to the memory controller. A power-saving control unit controls both a clock signal of an internal circuit of the memory controller and a clock enable signal of the SDRAM in response to a control signal supplied from the interface unit.

Inventors: Li; Jiang (Kawasaki, JP)

Assignee: Fujitsu Limited

International Classification: G06F 1/26 (20060101)

Expiration Date: 8/01/02018