Patent Number:
7,085,949
Title:
Method and related apparatus for locking phase with estimated rate modified by rate dithering
Abstract:
A method and related apparatus for providing a clock synchronized with an input signal. The method includes generating an estimated rate according to transitions in the input signal, processing a dithering step for updating the estimated rate by multiplying it with a predetermined ratio, and adjusting the frequency of the clock according to the updated estimated rate. The predetermined ratios used in repeated dithering steps are modified according to a predetermined rule such that the predetermined ratio is different when the dithering steps are repeated.
Inventors:
Mar; William (Taipei Hsien, TW), Wen; Luke (Taipei Hsien, TW)
Assignee:
VIA Technologies Inc.
International Classification:
G06F 1/12 (20060101)
Expiration Date:
8/01/02018