Patent Number: 7,086,015

Title: Method of optimizing RTL code for multiplex structures

Abstract: A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of: (a) receiving as input a first register transfer level code for an integrated circuit design; (b) receiving as input a user defined optimum multiplex structure; (c) analyzing the first register transfer level code to identify a critical multiplex structure; (d) partitioning the global multiplex structure into local multiplex structures each identical to the user defined optimum multiplex structure; and (e) generating as output a second register transfer level code for the integrated circuit design that replaces the global multiplex structure with the local multiplex structures.

Inventors: Lahner; Juergen (Sunnyvale, CA), Atkmakuri; Kiran (Sunnyvale, CA), Chaturvedula; Kavitha (San Jose, CA)

Assignee: LSI Logic Corporation

International Classification: G06F 17/50 (20060101)

Expiration Date: 8/01/02018