Patent Number: 7,086,018

Title: Electronic circuit design method, simulation apparatus and computer-readable storage medium

Abstract: An electronic circuit designing method analyzes noise with respect to a wiring pair, and automatically corrects the wiring pair by determining a spacing between wirings of the wiring pair so as to prevent generation of a noise error, if the noise error is detected based on the analysis of the noise.

Inventors: Ito; Noriyuki (Kawasaki, JP)

Assignee: Fujitsu Limited

International Classification: G06F 17/50 (20060101)

Expiration Date: 8/01/02018