Patent Number: 7,086,027

Title: Method and apparatus for constraint graph based layout compaction for integrated circuits

Abstract: A method of compacting a circuit layout includes determining a critical path of the circuit layout, the critical path having a length not less than a length of each other path of the circuit layout. The method further includes representing the critical path to include a plurality of vertices and a plurality of edges, each one of the vertices being coupled to another of the vertices by an edge, the plurality of vertices including a flexible vertex corresponding to a flexible element of the circuit layout, the plurality of edges including a first shear edge. The method further includes representing the flexible vertex to include a first jogging edge. The method further includes determining an optimal cutest of the graph of the critical path, the cutest including at least one of the group consisting of the first jogging edge and the first shear edge.

Inventors: Chiluvuri; Venkata K. R. (Austin, TX), Marchenko; Alexander Mikhailovich (Moscow, RU), Sotnikov; Mikhail Anatolievich (Moscow, RU)

Assignee: Freescale Semiconductor, Inc.

International Classification: G06F 17/50 (20060101)

Expiration Date: 8/01/02018