Patent Number: 7,087,350

Title: Method for combining via patterns into a single mask

Abstract: In a damascene process of fabricating an interconnect structure in an integrated circuit, a method for removing separate via layers is disclosed herein, which includes combining the via layers into a single mask.

Inventors: Wang; Hsiang Wei (Hsin Chu, TW)

Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.

International Classification: G01F 9/00 (20060101)

Expiration Date: 8/08/02018