Patent Number: 7,087,363

Title: Method of forming a top gate thin film transistor

Abstract: A method of forming a top gate thin film transistor (TFT). By performing photolithography using a first reticle, a photoresist layer having a thick photoresist layer portion and a thin photoresist layer portion is formed on a silicon layer in an active area. Thus, a channel layer and source/drain regions in a silicon island are defined by the same patterning process. In addition, a gate and an LDD region in the silicon island are defined by photolithography using a second reticle and a backside exposure process. Accordingly, the top gate TFT fabrication process of the present invention requires only two reticles, and thereby reduces costs.

Inventors: Chen; Chih-Chiang (Ilan, TW), Chuang; Ching-Sang (Hsinchu, TW), Chang; Jiun-Jye (Kaohsiung, TW)

Assignee: Industrial Technology Research Institute

International Classification: G03F 7/00 (20060101)

Expiration Date: 8/08/02018