Patent Number: 7,087,442

Title: Process for the formation of a spatial chip arrangement and spatial chip arrangement

Abstract: Process for the formation of a spatial chip arrangement having several chips (32, 36, 37, 38, 39) arranged in several planes and electrically connected to one another, in which the chips are connected via their peripheral connection surfaces (33) to assigned conducting paths (23) of a conducting-path structure (24, 25) arranged on at least one carrier substrate (21, 22) by the chips being arranged transverse to the longitudinal extent of the carrier substrate.

Inventors: Oppermann; Hans-Hermann (Berlin, DE), Zakel; Elke (Falkensee, DE), Azdasht; Ghassem (Berlin, DE), Kasulke; Paul (Berlin, DE)

Assignee: Pac Tech-Packaging Technologies GmbH

International Classification: G01R 31/26 (20060101); H01L 21/50 (20060101); H01L 21/66 (20060101); H01L 21/44 (20060101); H01L 21/48 (20060101)

Expiration Date: 8/08/02018