Patent Number: 7,087,452

Title: Edge arrangements for integrated circuit chips

Abstract: A method is provided for forming microelectronic devices. This may include providing a wafer device having metallization layers, a plurality of integrated circuits and a channel area provided around each of the integrated circuits. Materials from within each channel area may be removed by etching or by laser to form an air gap around a perimeter of each integrated circuit. Each air gap may prevent cracking and/or delamination problems caused by a subsequent dicing of the wafer device by a wafer saw into a plurality of devices.

Inventors: Joshi; Subhash M. (Hillsboro, OR), Leavy; Tom P. (Mullingar, IE), Arcot; Binny (West Linn, OR), He; Jun (Portland, OR)

Assignee: Intel Corporation

International Classification: H01L 21/00 (20060101)

Expiration Date: 8/08/02018