Patent Number: 7,087,500

Title: Charge trapping memory cell

Abstract: A memory cell includes a channel region between source/drain regions at the top side of a semiconductor body and is provided, transversely with respect to the longitudinal direction, with a bulge formed in the semiconductor material. This results in a uniform distribution of the strength of a radially directed electric field and avoids field strength spikes at lateral edges of the channel region. A storage layer sequence is situated between the channel region and the gate electrode as part of a word line.

Inventors: Lau; Frank (Bad Aibling, DE), Willer; Josef (Riemerling, DE)

Assignee: Infineon Technologies AG

International Classification: H01L 21/76 (20060101)

Expiration Date: 8/08/02018