Patent Number: 7,087,512

Title: Method for fabricating connection regions of an integrated circuit, and integrated circuit having connection regions

Abstract: A method for fabricating an integrated circuit connection region includes application of a dielectric to an integrated circuit with a connection region, application of a corrodible metalization layer to the dielectric, application of a protection device to the metalization layer, and removal of the protection device in a region around the connection region.

Inventors: Hedler; Harry (Germering, DE), Irsigler; Roland (Munich, DE), Meyer; Thorsten (Dresden, DE), Vasquez; Barbara (Orinda, CA)

Assignee: Infineon Technologies AG

International Classification: H01L 21/44 (20060101)

Expiration Date: 8/08/02018