Patent Number: 7,087,517

Title: Method to fabricate interconnect structures

Abstract: A method includes forming a barrier layer on a substrate surface including at least one contact opening; forming an interconnect in the contact opening; and reducing the electrical conductivity of the barrier layer. A method including forming a barrier layer on a substrate surface including a dielectric layer and a contact opening, depositing a conductive material in the contact opening, removing the conductive material sufficient to expose the barrier layer on the substrate surface, and reducing the electrical conductivity of the barrier layer. An apparatus including a circuit substrate including at least one active layer including at least one contact point, a dielectric layer on the at least one active layer, a barrier layer on a surface of the dielectric layer, a portion of the barrier layer having been transformed from a first electrical conductivity to a second different and reduced electrical conductivity, and an interconnect coupled to the at least one contact point.

Inventors: Andreyushchenko; Tatyana N. (Portland, OR), Cadien; Kenneth (Portland, OR), Fischer; Paul (Portland, OR), Dubin; Valery M. (Portland, OR)

Assignee: Intel Corporation

International Classification: H01L 21/4763 (20060101)

Expiration Date: 8/08/02018