Patent Number: 7,087,521

Title: Forming an intermediate layer in interconnect joints and structures formed thereby

Abstract: Methods of forming a microelectronic structure are described. Those methods include forming a first adhesion layer on a conductive layer, forming an intermediate layer on the first adhesion layer, and forming a barrier layer on the intermediate layer, wherein the intermediate layer includes a coefficient of thermal expansion that is approximately between the coefficient of thermal expansion of the first adhesion layer and the coefficient of thermal expansion of the barrier layer.

Inventors: Renavikar; Mukul P. (Chandler, AZ), Barnak; John P. (Newberg, OR)

Assignee: Intel Corporation

International Classification: H01L 21/44 (20060101)

Expiration Date: 8/08/02018