Patent Number: 7,087,943

Title: Direct alignment scheme between multiple lithography layers

Abstract: A method for directly aligning multiple lithography masking layers. The method may be used to fabricate a flash plus logic structure. The flash plus logic structure may comprise a flash memory cell, a logic cell and a transistor.

Inventors: Kau; Derchang (Cupertino, CA), Hasnat; Khaled (San Jose, CA), Lee; Everett (Los Altos, CA)

Assignee: Intel Corporation

International Classification: H01L 27/10 (20060101); H01L 29/73 (20060101)

Expiration Date: 8/08/02018