Patent Number: 7,087,954

Title: In service programmable logic arrays with low tunnel barrier interpoly insulators

Abstract: Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a second logic plan having a number of logic cells arranged in rows and columns that are interconnected to produce a number of logical outputs such that the in service programmable logic array implements a logical function. The logic cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al.sub.2O.sub.3, Ta.sub.2O.sub.5, TiO.sub.2, ZrO.sub.2, Nb.sub.2O.sub.5 and/or a Perovskite oxide tunnel barrier.

Inventors: Forbes; Leonard (Corvallis, OR)

Assignee: Micron Technology, Inc.

International Classification: H01L 29/788 (20060101)

Expiration Date: 8/08/02018