Patent Number: 7,087,983

Title: Manufacturing methods of semiconductor devices and a solid state image pickup device

Abstract: A manufacturing method of manufacturing a semiconductor device having a plurality of wiring layers. The method includes the steps of forming a wiring by a first wiring layer as a pattern by dividing a desired pattern into a plurality of patterns, connecting the divided patterns, and exposing them, wherein a position of the connection is formed in parallel with the wiring which is formed by the first wiring layer, and forming a wiring by a second wiring layer having an area which intersects the connecting position by a batch processing of exposure.

Inventors: Itano; Tetsuya (Tokyo, JP), Inui; Fumihiro (Kanagawa, JP), Ogura; Masanori (Kanagawa, JP)

Assignee: Canon Kabushiki Kaisha

International Classification: H01L 23/49 (20060101)

Expiration Date: 8/08/02018