Patent Number: 7,088,122

Title: Test arrangement for testing semiconductor circuit chips

Abstract: The invention relates to a test arrangement for testing semiconductor circuit chips, in which a test signal received via a primary test channel from a driver amplifier of an item of test equipment is distributed via parallel sub-channels to a plurality of inputs of one or more semiconductor circuit chips under test the test arrangement having signal buffering circuits arranged in each sub-channel that receive and buffer the test signal from the driver amplifier before feeding it to the inputs of the semiconductor circuit chip(s).

Inventors: Hartmann; Udo (Neuried, DE), Canaud; Thierry (Munchen, DE)

Assignee: Infineon Technologies AG

International Classification: G01R 31/28 (20060101); H03K 19/00 (20060101)

Expiration Date: 8/08/02018