Patent Number: 7,088,136

Title: Programmable logic device latch circuits

Abstract: Latch circuitry is provided for programmable logic regions on integrated circuits such as programmable logic device integrated circuits. A programmable logic device may have programmable logic regions based on programmable combinational logic circuits. Latch circuitry in a logic region may be provided between an output of a programmable combinational logic circuit in the logic region and an output of the logic region. When the latch circuitry is enabled, the latch circuitry performs the functions of a level-sensitive latch. When the latch circuitry is disabled, the latch circuitry acts as a passive data path. The passive data path may include only a single driver so that the latch circuitry adds essentially zero additional delay to the data produced by the combinational logic.

Inventors: Lewis; David (Toronto, CA)

Assignee: Altera Corporation

International Classification: H03K 19/173 (20060101); G06F 7/38 (20060101)

Expiration Date: 8/08/02018