Patent Number:
7,088,624
Title:
System of multiplexed data lines in a dynamic random access memory
Abstract:
A system of multiplexed data lines in a DRAM integrated circuit includes a switching circuit having two switching states. In one switching state, the data lines connect to a first configuration of data paths as would occur in a typical DRAM integrated circuit. A limited number of spare column select lines are available to repair defective column select lines in the first configuration. In another switching state, the data lines connect to a second configuration of the data paths, doubling the number of spare column select lines available to repair a defective column select line.
Inventors:
Daniel; Alan (Durham, NC), Kunce; Christopher W. (Wake Forest, NC)
Assignee:
Infineon Technologies, A.G.
International Classification:
G11C 16/04 (20060101)
Expiration Date:
8/08/02018