Patent Number: 7,088,797

Title: Phase lock loop with cycle drop and add circuitry

Abstract: Phase locked loops that can adjust the frequency of a clock signal are provided. A transmitter adjusts its data transmission rate in response to the clock signal to accommodate different data transmission protocols. A phase locked loop can add or drop cycles from an input clock signal in response to one or more signals from a receiver. The signals from the receiver indicate the transmission rate of the incoming data signal. The phase locked loop can drop cycles from the clock signal to decrease the frequency of the clock signal. The transmitter then decreases its data transmission rate in response to the reduced frequency of the clock signal. The phase locked loop can also add cycles to the clock signal to increase the frequency of the clock signal. The transmitter increases its data transmission rate in response to the increased frequency of the clock signal.

Inventors: Momtaz; Afshin (Irvine, CA), Chung; David Kyong-Sik (Newport Beach, CA), Hsu; Pang-Cheng (Irvine, CA)

Assignee: Broadcom Corporation

International Classification: H03D 3/24 (20060101); H03L 7/06 (20060101)

Expiration Date: 8/08/02018